1. Field of the Invention
The present invention relates generally to microscopic inspection methods and apparatus. The present invention relates more particularly to automated inspection systems for semiconductor manufacturing.
2. Description of the Background Art
A variety of methods have been used to examine microscopic surface structures of semiconductors. These have important applications in the field of semiconductor integrated circuit (IC) fabrication, where microscopic defects at a surface layer make the difference between a good or bad IC. For example, holes or vias in an intermediate insulating layer often provide a physical conduit for an electrical connection between two outer conducting layers. If one of these holes or vias becomes clogged, it will be impossible to establish this electrical connection. Automated inspection of the semiconductors is used to ensure a level of quality control in the manufacture of the integrated circuits.
An example of an electron beam (e-beam) apparatus for an inspection system is described in U.S. Pat. No. 5,578,821, issued to Meisberger et al (the Meisberger patent). The disclosure of the Meisberger patent is hereby incorporated by reference in its entirety. FIG. 1 (corresponding to FIG. 5 in the Meisberger patent) is a simplified schematic representation of the paths of the primary, secondary, back-scatter and transmitted electrons through the electron column and collection system for electron beam inspection. In brief, FIG. 1 shows a schematic diagram of the various electron beam paths within the column and below substrate 57. Electrons are emitted radially from field emission cathode 81 and appear to originate from a very small bright point source. Under the combined action of the accelerating field and condenser lens magnetic field, the beam is collimated into a parallel beam. Gun anode aperture 87 masks off electrons emitted at unusable angles, while the remaining beam continues on to beam limiting aperture 99. An upper deflector (not depicted) is used for stigmation and alignment, ensuring that the final beam is round and that it passes through the center of the objective lens 104 comprising elements 105, 106 and 107. A condenser lens (not depicted) is mechanically centered to the axis defined by cathode 81 and beam limiting aperture 99. The deflection follows the path shown, so that the scanned, focused probe (beam at point of impact with the substrate) emerges from the objective lens 104. In High Voltage mode operation, Wien filter deflectors 112 and 113 deflect the secondary electron beam into the secondary electron detector 117. When partially transparent masks are imaged, the transmitted beam 108 passes through electrode system 123 and 124 that spreads the beam 108 before it hits the detector 129. In Low Voltage mode operation, the secondary electron beam is directed by stronger Wien filter deflections toward the low-voltage secondary electron detector 160 that may be the same detector used for backscatter imaging at high voltage. Further detail on the system and its operation is described in the Meisberger patent.
FIG. 2 is a schematic depiction of a multitude of integrated circuit (IC) dies for manufacture on a single semiconductor wafer. The semiconductor wafer 202 typically comprises a silicon wafer. The wafer 202 may be, for example, 200 mm or 300 mm in diameter. On the surface of the wafer 202, numerous integrated circuit dies 204 are manufactured thereon. The integrated circuits may comprise, for example, microprocessors, memories, digital logic, analog circuits, and other circuitry.
FIG. 3 is a schematic depiction illustrating conventional raster scanning of a conventional e-beam across a semiconductor die. The typical e-beam apparatus, such as the one depicted in FIG. 1, raster scans the e-beam across an area of a specimen to generate an image thereof (much like a conventional television raster scans a beam across the screen to generate an image frame). An example path 302 of such raster scanning across an integrated circuit die 204 is illustrated in FIG. 3.
FIG. 4 is a schematic depiction illustrating a conventional translation path 402 of a semiconductor wafer 202 under an e-beam column. The translation of the wafer under the raster-scanned e-beam may be performed, for example, in steps such that one portion of a wafer is scanned, then an adjacent portion, and so on, until all the integrated circuits 204 on the wafer have been scanned. Alternatively, if only a fraction of the integrated circuits 204 are to be inspected, the path 402 need cover only those ICs to be inspected. In either case, the translation path fully spans the area to be inspected.